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請問有新埔站的立體圖嗎? guest 請問有新埔站的立體圖嗎? 2013/10/27 17:49

請問有新埔站的立體圖嗎?
謝謝

訪客 guest 訪客 2014/03/04 22:26

大安森林公園站也畫畫看嘛～

daniel101812 daniel101812 2017/03/06 11:14

加油，超實用

訪客 guest 訪客 2017/03/06 13:01

借分享，感謝！

劉奕辰 facebook 劉奕辰 2017/03/06 20:10

真的很棒，借分享

bravobear Sunny Wen 2017/07/31 16:23

想詢問您是否願意做導覽圖?
請與我聯繫 謝謝

中央大學秘書室 溫小姐
03-422-7151#57013

訪客 guest 訪客 2018/04/21 23:35

有考慮畫與機捷交會的三重站嗎~

訪客 guest 訪客 2020/06/07 00:13

請問有小港機場站的嗎?

Mao Mei-Neng facebook Mao Mei-Neng 2020/07/30 15:06

您好，不知道是否能在學術文章中使用您所繪製的轉乘車站立體圖呢？會清楚標明出處，先謝謝您的撥冗回應！

訪客 guest 訪客 2020/11/23 15:14

您好，請問有考慮畫高鐵台中站與新烏日站 中捷高鐵台中站 三鐵車站的立體圖嗎~

葉青峻 guest 葉青峻 2021/03/10 09:27

常見的半導體材料有矽、鍺、砷化鎵等
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晶片測試
晶片處理高度有序化的本質增加了對不同處理步驟之間度量方法的需求。晶片測試度量裝置被用於檢驗晶片仍然完好且沒有被前面的處理步驟損壞。如果If the number of dies—the 積體電路s that will eventually become chips—當一塊晶片測量失敗次數超過一個預先設定的閾值時，晶片將被廢棄而非繼續後續的處理製程。
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晶片測試
晶片處理高度有序化的本質增加了對不同處理步驟之間度量方法的需求。晶片測試度量裝置被用於檢驗晶片仍然完好且沒有被前面的處理步驟損壞。如果If the number of dies—the 積體電路s that will eventually become chips—當一塊晶片測量失敗次數超過一個預先設定的閾值時，晶片將被廢棄而非繼續後續的處理製程。

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步驟列表

晶片處理
濕洗
平版照相術
光刻Litho
離子移植IMP
蝕刻（干法蝕刻、濕法蝕刻、電漿蝕刻）
熱處理
快速熱退火Annel
熔爐退火
熱氧化
化學氣相沉積 (CVD)
物理氣相沉積 (PVD)
分子束磊晶 (MBE)
電化學沉積 (ECD)，見電鍍
化學機械平坦化 (CMP)

IC Assembly and Testing 封裝測試
Wafer Testing 晶片測試
Visual Inspection外觀檢測
Wafer Probing電性測試
FrontEnd 封裝前段
Wafer BackGrinding 晶背研磨
Wafer Mount晶圓附膜
Wafer Sawing晶圓切割
Die attachment上片覆晶
Wire bonding焊線
BackEnd 封裝後段
Molding模壓
Post Mold Cure後固化
De-Junk 去節
Plating 電鍍
Marking 列印
Trimform 成形
Lead Scan 檢腳
Final Test 終測
Electrical Test電性測試
Visual Inspection光學測試
Baking 烘烤
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有害材料標誌

許多有毒材料在製造過程中被使用。這些包括：

有毒元素摻雜物比如砷、硼、銻和磷
有毒化合物比如砷化三氫、磷化氫和矽烷
易反應液體、例如過氧化氫、發煙硝酸、硫酸以及氫氟酸

工人直接暴露在這些有毒物質下是致命的。通常IC製造業高度自動化能幫助降低暴露於這一類物品的風險。
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Device yield

Device yield or die yield is the number of working chips or dies on a wafer, given in percentage since the number of chips on a wafer (Die per wafer, DPW) can vary depending on the chips' size and the wafer's diameter. Yield degradation is a reduction in yield, which historically was mainly caused by dust particles, however since the 1990s, yield degradation is mainly caused by process variation, the process itself and by the tools used in chip manufacturing, although dust still remains a problem in many older fabs. Dust particles have an increasing effect on yield as feature sizes are shrunk with newer processes. Automation and the use of mini environments inside of production equipment, FOUPs and SMIFs have enabled a reduction in defects caused by dust particles. Device yield must be kept high to reduce the selling price of the working chips since working chips have to pay for those chips that failed, and to reduce the cost of wafer processing. Yield can also be affected by the design and operation of the fab.

Tight control over contaminants and the production process are necessary to increase yield. Contaminants may be chemical contaminants or be dust particles. "Killer defects" are those caused by dust particles that cause complete failure of the device (such as a transistor). There are also harmless defects. A particle needs to be 1/5 the size of a feature to cause a killer defect. So if a feature is 100 nm across, a particle only needs to be 20 nm across to cause a killer defect. Electrostatic electricity can also affect yield adversely. Chemical contaminants or impurities include heavy metals such as Iron, Copper, Nickel, Zinc, Chromium, Gold, Mercury and Silver, alkali metals such as Sodium, Potassium and Lithium, and elements such as Aluminum, Magnesium, Calcium, Chlorine, Sulfur, Carbon, and Fluorine. It is important for those elements to not remain in contact with the silicon, as they could reduce yield. Chemical mixtures may be used to remove those elements from the silicon; different mixtures are effective against different elements.

Several models are used to estimate yield. Those are Murphy's model, Poisson's model, the binomial model, Moore's model and Seeds' model. There is no universal model; a model has to be chosen based on actual yield distribution (the location of defective chips) For example, Murphy's model assumes that yield loss occurs more at the edges of the wafer (non-working chips are concentrated on the edges of the wafer), Poisson's model assumes that defective dies are spread relatively evenly across the wafer, and Seeds's model assumes that defective dies are clustered together.[25]

Smaller dies cost less to produce (since more fit on a wafer, and wafers are processed and priced as a whole), and can help achieve higher yields since smaller dies have a lower chance of having a defect. However, smaller dies require smaller features to achieve the same functions of larger dies or surpass them, and smaller features require reduced process variation and increased purity (reduced contamination) to maintain high yields. Metrology tools are used to inspect the wafers during the production process and predict yield, so wafers predicted to have too many defects may be scrapped to save on processing costs.[26]

Peter Lee facebook Peter Lee 2021/03/16 15:18

請問有橋和站、凱旋站以及西子灣站的立體圖嗎?謝謝